Principal ASIC Design Engineer (PCI Express)
Job ID: JOB-13035
As a member of Our client’s engineering community, your primary responsibility will be to design, simulate, and verify the PCI Express supporting digital logic solutions for an advanced ASIC or FPGA. Our client’s designs are an SOC with various Hard and Soft IP blocks that support a large number of industry standard protocols.
Duties & Responsibilities
- General RTL and ASIC development
- Detailed module design, performance analysis and detailed design specification creation
- Participate in the RTL implementation, synthesis, formality check as well as ECOs
- Support post-layout timing closure and verification
- Participate in the investigation & assessment of emerging SerDes/Transceiver technologies & IPs
- Improve Data & Command processing bandwidth, reduce latencies & increase reliability
- Support porting the design into test chips and emulation platforms
- Support pre-tapeout verification and post-tapeout validation/characterization of the system designed
- Work closely with FPGA support software and FW engineers to resolve hardware issues and customer issues
- PCI-Express Development
- Integrate PCI Express logic into a final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps.
- Work with 3rd party vendors for evaluation of potential IP cores and work with those IP providers to ensure robust, high bandwidth solutions.
- Develop Block Level Constraints and run synthesis
- Perform Static Timing Analysis of the PCI Express digital logic and review post-layout timing.
- Support Verification and Validation groups in testing of the IP blocks and other similar logic blocks.
- Integrate and simulate memory controller designs including – Integration into processor sub-systems as needed and Integration into IP used in the FPGA fabric of the device.
- Develop and/or integrate to industry standard Memory Controller Protocols – PCI-Express and related protocols such as CCIX and CXL and Other add-on protocols such as NVMe are a plus
- Ongoing customer support to ensure the IP cores are robust with performance that meets the customer performance and/or power goals.
- Support RTL design engineers with less experience for the functions shown above
- Bachelors/Master’s in electrical engineering, Computer Engineering or Computer Science.
- Minimum of 10 years of proven silicon design experience in high speed RTL design of PCI-Express, Ethernet and other related logic.
- Experience is SOC IP development for PCI-Express and associated protocols.
- Strong Experience in RTL design, design verification, synthesis & formality.
- Strong Experience in Static Timing Analysis and Verilog simulation tools.
- FPGA and ASIC System On Chip Design Experience.
- Lab Experience for System Level Validation.
- Ability to design complex state machines & data path logic.
- Ability to write detailed design specifications.
- Good analytical, oral, and written communication skills.
- Able to write clean, readable presentations.
- Self-motivated, proactive team player.
- Ability to work to schedule requirements.
For further information on this role in Analog Design Engineering please contact Michael Brennan on Hire@hero.ie or 086-440 3742
Check out all our open jobs on our HERO Recruitment website – https://www.hero.ie/
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Data can only be transferred outside of the EEA on the basis of standards contractual clauses, to a country for whom an adequacy decision has been given by the European Commission or where the express permission of the data subject has been given. You have supplied us with your personal data in the process of applying for a position. Our client company may have personnel outside of the EEA who will review you data. We will apply the appropriate criteria in respect of the data transfer depending on the location of those personnel.
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